Exemplary embodiments relate to a semiconductor memory device and an operating method thereof and, more particularly, to a semiconductor memory device including non-volatile memory cells and an operating method thereof.
As the size of a memory cell is reduced in non-volatile memory devices, such as NAND flash memory devices, an interference phenomenon may more easily occur between adjacent memory cells when a program operation is performed. Accordingly, the threshold voltages of memory cells adjacent to a programmed memory cell are greatly shifted by the interference phenomenon. Furthermore, the distribution of the threshold voltages of memory cells programmed in a target level is widened by the interference phenomenon, and an interval between the distributions of the threshold voltages of memory cells programmed in different levels is narrowed. Consequently, data stored in a memory cell may not be read properly, for example, different data may be read. This phenomenon is further increased in a Multi-Level Cell (hereinafter referred to as an ‘MLC’) program method of storing data of 2 bits in one memory cell.
There are being proposed several methods of reducing the interference phenomenon between the memory cells in the MLC program operation. One of the methods is described below.
FIGS. 1A and 1B are diagrams illustrating the distributions of the threshold voltages of memory cells which are shifted by the program operation of a semiconductor memory device.
Referring to FIG. 1A, data of 2 bits includes Least Significant Bit (hereinafter referred to as an ‘LSB’) data and Most Significant Bit (hereinafter referred to as an ‘MSB’) data. The data of 2 bits is stored in a memory cell by an LSB program operation for storing the LSB data and an MSB program operation for storing the MSB data. First, when the LSB program operation is performed, the threshold voltages of first cells and second cells, from among first to fourth memory cells coupled to a selected word line, rise. Here, the first cells and the second cells may be cells to which data ‘0’ is inputted as the LSB data,
Referring to FIG. 1B, when the MSB program operation is performed, the threshold voltages of the third cells, from among the first to fourth memory cells coupled to the selected word line, rise to a first level PV1, the threshold voltages of the second cells rise to a second level PV2, and the threshold voltages of the first cells rise to a third level PV3. Here, the third cells and the first cells may be cells to which data ‘0’ is inputted as the MSB data.
Thus, the threshold voltages of the first to fourth memory cells are distributed over the four different levels PV0, PV1, PV2, and PV3 depending on the data of 2 bits stored by the LSB program operation and the MSB program operation.
The lowest level A and the highest level B of a threshold voltage distribution of the fourth cells that are to maintain an erase level PV0 rise owing to an interference phenomenon occurring when the MSB program operation is performed. Since the threshold voltages of the third cells are greatly shifted from the erase level PV0 to the first level PV1, the rise of the threshold voltages of the third cells becomes a major cause of the rise in the threshold voltage distribution of the fourth cells.
Meanwhile, when the highest level B of the threshold voltage distribution of the fourth cells is higher than 0 V owing to the interference phenomenon, a margin between the threshold voltage distribution of the first cells and the threshold voltage distribution of the fourth cells is reduced. For this reason, an interval between a threshold voltage distribution of the second cells and a threshold voltage distribution of the third cells is narrowed. As a result, a sensing margin for distinguishing the threshold voltages of the second cells and the threshold voltages of the third cells from each other is reduced. In severe cases, an error in the operation may occur.